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74VHCT574A
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING
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HIGH SPEED: fMAX = 180 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA=25C COMPATIBLE WITH TTL OUTPUTS: VIH = 2V (MIN.), VIL = 0.8V (MAX) POWER DOWN PROTECTION ON INPUTS & OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC(OPR) = 4.5V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 574 IMPROVED LATCH-UP IMMUNITY LOW NOISE: VOLP = 0.9V (MAX.)
SOP
TSSOP
Table 1: Order Codes
PACKAGE SOP TSSOP T&R 74VHCT574AMTR 74VHCT574ATTR
DESCRIPTION The 74VHCT574A is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. These 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE). On the positive transition of the clock, the Q outputs will be set to the logic states that were setup at the D inputs. Figure 1: Pin Connection And IEC Logic Symbols
When the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and when (OE) is high, the outputs will be in a high impedance state. The Output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V since all inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
December 2004
Rev. 4
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Figure 2: Input Equivalent Circuit Table 2: Pin Description
PIN N 1 2, 3, 4, 5, 6, 7, 8, 9 12, 13, 14, 15, 16, 17, 18, 19 11 10 20 SYMBOL OE D0 to D7 Q0 to Q7 NAME AND FUNCTION 3-State Output Enable Input (Active LOW) Data Inputs 3-State Outputs
CK GND VCC
Clock Input (LOW-to-HIGH Edge Triggered) Ground (0V) Positive Supply Voltage
Table 3: Truth Table
INPUTS OE H L L L
X : Don't Care Z : High Impedance
OUTPUT D X X L H Q Z NO CHANGE L H
CK X
Figure 3: Logic Diagram
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Table 4: Absolute Maximum Ratings
Symbol VCC VI VO VO IIK IOK IO Supply Voltage DC Input Voltage DC Output Voltage (see note 1) DC Output Voltage (see note 2) DC Input Diode Current DC Output Diode Current DC Output Current Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V V mA mA mA mA C C
ICC or IGND DC VCC or Ground Current Storage Temperature Tstg TL Lead Temperature (10 sec)
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied 1) Output in OFF State 2) High or Low State
Table 5: Recommended Operating Conditions
Symbol VCC VI VO VO Top dt/dv Supply Voltage Input Voltage Output Voltage (see note 1) Output Voltage (see note 2) Operating Temperature Input Rise and Fall Time (see note 3) (VCC = 5.0 0.5V) Parameter Value 4.5 to 5.5 0 to 5.5 0 to 5.5 0 to VCC -55 to 125 0 to 20 Unit V V V V C ns/V
1) Output in OFF State 2) High or Low State 3) VIN from 0.8V to 2V
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Table 6: DC Specifications
Test Condition Symbol Parameter VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 4.5 4.5 4.5 4.5 to 5.5 0 to 5.5 5.5 5.5 0 IO=-50 A IO=-8 mA IO=50 A IO=8 mA VI = VIH or VIL VO = 0V to 5.5V VI = 5.5V or GND VI = VCC or GND One Input at 3.4V, other input at VCC or GND VOUT = 5.5V TA = 25C Min. 2 0.8 4.4 3.94 0.0 0.1 0.36 0.25 0.1 4 1.35 0.5 4.5 4.4 3.8 0.1 0.44 2.5 1.0 40 1.5 5.0 Typ. Max. Value -40 to 85C Min. 2 0.8 4.4 3.7 0.1 0.55 2.5 1.0 40 1.5 5.0 Max. -55 to 125C Min. 2 0.8 Max. V V V V A A A mA A Unit
VIH VIL VOH VOL IOZ
High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage High Impedance Output Leakage Current Input Leakage Current Quiescent Supply Current Additional Worst Case Supply Current Output Leakage Current
II ICC +ICC
IOPD
Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)
Test Condition Symbol Parameter VCC (V) 5.0(*) 5.0(*) 5.0(*) 5.0
(*)
Value TA = 25C Min. Typ. 5.5 7.0 5.0 6.0 7.0 90 85 140 130 1.5 1.5 1.5 Max. 8.6 10.6 9.0 11.0 10.1 -40 to 85C Min. 1.0 1.0 1.0 1.0 1.0 80 Max. 10.0 12.0 10.5 12.5 11.5 -55 to 125C Min. 1.0 1.0 1.0 1.0 1.0 80 Max. 10.0 12.0 10.5 12.5 11.5 ns Unit
CL (pF) 15 50 15 50 50 15 50 50 RL = 1K RL = 1K
tPLH tPHL tPZL tPZH tPLZ tPHZ fMAX tOSLH tOSHL
Propagation Delay Time CK to Q Output Enable Time Output Disable Time Maximum Clock Frequency Output to Output Skew time (note 1)
ns ns MHz ns
5.0(*) 5.0(*) 5.0
(*)
5.0(*)
(*) Voltage range is 5.0V 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm - tpLHn|, tsoHL = |tpHLm - tpHLn|
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Table 8: Capacitive Characteristics
Test Condition Symbol Parameter TA = 25C Min. CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) Typ. 4 9 25 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF pF Unit
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC/8 (per Flip-Flop)
Table 9: Dynamic Switching Characteristics
Test Condition Symbol Parameter VCC (V) 5.0 TA = 25C Min. Typ. 1.2 -1.6 CL = 50 pF 3.5 -1.2 V Max. 1.6 Value -40 to 85C Min. Max. -55 to 125C Min. Max. Unit
VOLP VOLV VIHD
VILD
Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3)
5.0
5.0
1.5
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.0V, (n-1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
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Figure 4: Test Circuit
TEST tPLH, tPHL tPZL, tPLZ tPZH, tPHZ
CL =15/50pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K or equivalent RT = ZOUT of pulse generator (typically 50)
SWITCH Open VCC GND
Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
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Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
Figure 7: Waveform - Pulse Width (f=1MHz; 50% duty cycle)
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SO-20 MECHANICAL DATA
DIM. A A1 B C D E e H h L k ddd 10.00 0.25 0.4 0 mm. MIN. 2.35 0.1 0.33 0.23 12.60 7.4 1.27 10.65 0.75 1.27 8 0.100 0.394 0.010 0.016 0 TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 8 0.004 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299
0016022D
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TSSOP20 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 6.4 6.2 4.3 6.5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 6.6 6.6 4.48 0.002 0.031 0.007 0.004 0.252 0.244 0.169 0.256 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0079 0.260 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0087225C
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Tape & Reel SO-20 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 10.8 13.2 3.1 3.9 11.9 12.8 20.2 60 30.4 11 13.4 3.3 4.1 12.1 0.425 0.520 0.122 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 1.197 0.433 0.528 0.130 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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Tape & Reel TSSOP20 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 6.8 6.9 1.7 3.9 11.9 12.8 20.2 60 22.4 7 7.1 1.9 4.1 12.1 0.268 0.272 0.067 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.276 0.280 0.075 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
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Table 10: Revision History
Date 16-Dec-2004 Revision 4 Description of Changes Order Codes Revision - pag. 1.
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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